Full-Chip Nanometer Routing Techniques
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...
| Main Authors: | , , |
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| Corporate Author: | |
| Language: | English |
| Published: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2007.
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| Edition: | 1st ed. 2007. |
| Series: | Analog Circuits and Signal Processing,
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| Subjects: | |
| Online Access: | https://doi.org/10.1007/978-1-4020-6195-0 |