CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...
| Main Authors: | , |
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| Corporate Author: | |
| Language: | English |
| Published: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
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| Edition: | 1st ed. 2008. |
| Series: | Frontiers in Electronic Testing,
40 |
| Subjects: | |
| Online Access: | https://doi.org/10.1007/978-1-4020-8363-1 |
Table of Contents:
- and Motivation
- SRAM Circuit Design and Operation
- SRAM Cell Stability: Definition, Modeling and Testing
- Traditional SRAM Fault Models and Test Practices
- Techniques for Detection of SRAM Cells with Stability Faults
- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.