High-Level Synthesis from Algorithm to Digital Circuit /
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be ef...
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| Other Authors: | , |
| Language: | English |
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Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
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| Edition: | 1st ed. 2008. |
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| Online Access: | https://doi.org/10.1007/978-1-4020-8588-8 |