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Low Power Methodology Manual For System-on-Chip Design /

"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to...

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Main Authors: Flynn, David. (Author, http://id.loc.gov/vocabulary/relators/aut), Aitken, Rob. (http://id.loc.gov/vocabulary/relators/aut), Gibbons, Alan. (http://id.loc.gov/vocabulary/relators/aut), Shi, Kaijian. (http://id.loc.gov/vocabulary/relators/aut)
Corporate Author: SpringerLink (Online service)
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2007.
Edition:1st ed. 2007.
Series:Integrated Circuits and Systems,
Subjects:
Electronic circuits.
Electronics.
Microelectronics.
Electrical engineering.
Computer hardware.
Circuits and Systems.
Electronics and Microelectronics, Instrumentation.
Electrical Engineering.
Computer Hardware.
Online Access:https://doi.org/10.1007/978-0-387-71819-4
Table of Contents:
  • Standard Low Power Methods
  • Multi-Voltage Design
  • Power Gating Overview
  • Designing Power Gating
  • Architectural Issues for Power Gating
  • A Power Gating Example
  • IP Design for Low Power
  • Frequency and Voltage Scaling Design
  • Examples of Voltage and Frequency Scaling Design
  • Implementing Multi-Voltage, Power Gated Designs
  • Physical Libraries
  • Retention Register Design
  • Design of the Power Switching Network.

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