Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) / by Sridhar Gangadharan, Sanjay Churiwala.

by Gangadharan, Sridhar., Gangadharan, Sridhar., Churiwala, Sanjay.
Published 2013

Designing with Xilinx® FPGAs Using Vivado / edited by Sanjay Churiwala.

Published 2017