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High Performance Multi-Channel High-Speed I/O Circuits

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at highe...

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Main Authors: Oh, Taehyoun. (Author, http://id.loc.gov/vocabulary/relators/aut), Harjani, Ramesh. (http://id.loc.gov/vocabulary/relators/aut)
Corporate Author: SpringerLink (Online service)
Language:English
Published: New York, NY : Springer New York : Imprint: Springer, 2014.
Edition:1st ed. 2014.
Series:Analog Circuits and Signal Processing,
Subjects:
Electronic circuits.
Electronics.
Microelectronics.
Microwaves.
Optical engineering.
Circuits and Systems.
Electronics and Microelectronics, Instrumentation.
Microwaves, RF and Optical Engineering.
Online Access:https://doi.org/10.1007/978-1-4614-4963-8
Table of Contents:
  • Introduction
  • 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process
  • 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process
  • Adaptive XTCR, AGC, and Adaptive DFE Loop
  • Research Summary & Contributions
  • References
  • Appendix A: Noise Analysis
  • Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4)
  • Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter
  • Appendix D: Line Mismatch Sensitivity
  • Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench
  • Appendix F: Bandwidth Improvement by Technology Scaling.

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